DRAM devices are memory devices that require repeated refreshing of the storage cells in a bank of memory cells. Bit line sensing current is a major part of the self-refreshing process. The self-refresh current is an important performance factor for mobile or portable DRAM devices, because the self-refresh current is directly related to battery performance of the mobile or portable host device.
FIGS. 1 and 2 illustrate a prior art bit line sensing arrangement for a cell array. There is a plurality of bit line sensing amplifier (BLSA) blocks 0–n, assigned reference numerals 5(0) to 5(N), respectively. Each BLSA block comprises a BLSA 10(j) for each column (j=0 to M) of the storage cell array. There is a BLSA block located at both sides of a cell array, as is known in the art. Each BLSA 10(j) associated with a particular column is connected to a bit line (BL) and a BL complement (/BL). FIG. 1 has been simplified and does not show the cell arrays, and the BL and /BL are shown for only one BLSA 10(0).
Each BLSA block has a PMOS source node (PS) and an NMOS source node (NS) that are electrically connected to each BLSA throughout a BLSA block. Transistors MP0 and MN0 charge and discharge the PS and NS, respectively, after the wordlines (WLs) are activated. An equalization circuit 20 included in each BLSA block is controlled by an equalization control signal (EQ) and in response sets the voltages at PS and NS equal to VBLEQ during precharge.
With reference to FIG. 2, during precharge, the EQ signal stays high, and as a result all BLs are at VBLEQ. PSET and NSET are control signals that activate the BLSAs. To activate a BLSA block, PSET goes from high to low and NSET goes from low to high. During an activate interval, the voltage at PS goes from VBLEQ to VBLH and the voltage at NS from VBLEQ to ground (GND). The problem with the prior art bit line sensing configuration described above is that a significant amount of sensing current is used for bit line sensing. Again, since this current is used during self-refresh, there is a significant impact on the battery performance when the DRAM is used in a mobile or portable device.
It is desirable to reduce the amount of sensing current during a self-refresh mode of a DRAM device, to thereby reduce current drain on the host device in which the DRAM device resides.